Intel delays higher-end ‘Broadwell’ chips to July – September, 2015

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Intel Corp. has reconsidered the launch schedule of its next-generation microprocessors code-named “Broadwell” and further delayed not only mainstream mobile parts, but also the high-end desktop and notebook models. Based on the new plan, the company may introduce the new Core i-series microprocessors only in July, or even September, 2015.

Previously Intel planned to release the Broadwell-H series of chips with two or four cores and advanced Iris Pro graphics engines during the ww21 2015 – ww26 2015 launch window, which is mid-May – late-June. However, according to a revised schedule published by Chinese VR-Zone web-site, the new availability window for the Broadwell-H processors for desktops and high-performance notebooks is ww29 2015 – ww36 2015, which is mid-July – early-September.

intel core m broadwell shipments schedule1 1024x742 Intel delays higher end ‘Broadwell’ chips to July – September, 2015

As previously reported, the code-named Skylake microprocessors will co-exist with the Broadwell chips on the market. While exact launch plans concerning the Skylake chips, which will rely on brand-new platforms, are unclear (except the fact that they will be available in the Q2 2015), it is possible that the SKL central processing units will emerge on the market earlier than the most powerful models from the Broadwell family of CPUs.

The most advanced versions of Intel Broadwell microprocessors for client PCs will feature up to four x86 cores with Hyper-Threading, Iris Pro graphics processors with up to 48 execution units, up to 8MB of L3 cache, up to 128MB of high-speed eDRAM off-die cache, dual-channel DDR3 memory controllers and so on. The chips are expected to be available in BGA and LGA1150 form-factors. Exact configurations look as follows:

  • BDW-H 4+3e BGA: four cores with or without HT, Iris Pro GT3e graphics core with 48 execution units and 128MB eDRAM, 6MB of 8MB L3.
  • BDW-H 4+2 BGA: four cores with or without HT, Intel HD Graphics GT2 graphics core with 24 execution units, 6MB of 8MB L3.
  • BDW-H 2+3e BGA: two cores with or without HT, Iris Pro GT3e graphics core with 48 execution units and 128MB eDRAM, 4MB L3.
  • BDW-H 4+3e LGA: four cores with or without HT, Iris Pro GT3e graphics core with 48 execution units and 128MB eDRAM, 6MB of 8MB L3.

It is believed that Intel has run into major yield issues with its 14nm fabrication process. It is unclear whether the Skylake microprocessors are also affected by the same problems. Typically Intel tailors designs of its chips to peculiarities of its process technologies, which is why it is possible that yields of the Skylake CPUs will be higher compared to the yields of the Broadwell family. Keeping in mind that the former is also expected to offer higher performance than the latter, it is unclear why Intel needs the Broadwell at all.

intel broadwell skylake1 1024x514 Intel delays higher end ‘Broadwell’ chips to July – September, 2015

Intel did not comment on the news-story.

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KitGuru Says: At present Intel’s roadmap looks somewhat illogical when it concerns high-performance solutions for client PCs. The Skylake platform simply must be more advanced than the Broadwell platform and the former is currently expected to be released in the second quarter of 2015, at least several weeks ahead of the Broadwell-H. Intel is expected to artificially position the Broadwell-K unlocked chips above the Skylake-S products. While this would work if Intel releases the chips simultaneously, it will unlikely work if the Broadwell-H/Broadwell-K are significantly late. Once PC makers start to adopt the Skylake-S in the Q2 (which means that the majority of their back-to-school systems will feature the Skylake-S), they and Intel will start to advertise the advantages of the platform, which will inevitably lower demand for the Broadwell chips. Perhaps, it is logical for Intel to simply cancel the Broadwell products for high-end systems and focus on Skylake? Of course, if the Skylake is healthy.

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  • Yeltnerb1

    Reducing of the L3 cache from 8MB to 6MB for the highest-end model would be a FAIL >_<

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