AMD's upcoming Strix Point and Strix Halo APUs are generating some buzz in the community. While AMD has yet to reveal the complete specifications for its next-generation APUs based on Zen 5 architecture, a new leak has given us much more information.

According to the documents obtained by HKEPC (via VideoCardz), the Strix Point will pack 12 Zen 5 cores and 24 threads. The APU includes 8 WGP (Work Group Processors) based on the RDNA 3.5 architecture, which should convert to 16 CUs. Based on the FP8 socket, these APUs will also feature 12MB of L2 cache, 24MB of L3 cache, and an XDNA 2 AI-Accelerator, which promises to deliver 50 TOPS (trillion operations per second). Moreover, Strix Point APUs support DisplayPort 2.1 and UHBR10 mode and has 16 PCIe Gen4 lanes and a TDP of up to 65W.

Image credit: HKEPC

Moving on to Strix Halo, the specifications reveal 16 cores and 32 threads based on the Zen 5 architecture. The APU comes with 1MB of L2 cache per core, resulting in 16MB of L2 cache and 32MB of unified L3 cache per CCD. The Strix Halo also features the XDNA 2 processor for AI, with up to 60 TOPS, and supports up to DP 2.1 UHBR20 mode. Unlike Strix Point, Strix Halo has a default TDP of 70W that can go up to 130W, and it's based on the FP11 socket. It also supports 256-bit LPDDR5X-8000 memory. Lastly, these APUs will pack 32MB of MALL Cache, which supposedly works similarly to Infinity Cache.

AMD is expected to give a keynote at Computex 2024 (running from June 4th to June 7th), which may include more details about the upcoming Zen 5-based desktops and mobile devices.

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KitGuru says: How much of an upgrade do you expect the Strix Point and Halo will bring over the current AMD APUs?

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