512-bit | KitGuru https://www.kitguru.net KitGuru.net - Tech News | Hardware News | Hardware Reviews | IOS | Mobile | Gaming | Graphics Cards Mon, 02 Mar 2015 21:56:58 +0000 en-US hourly 1 https://wordpress.org/?v=6.4.3 https://www.kitguru.net/wp-content/uploads/2021/06/cropped-KITGURU-Light-Background-SQUARE2-32x32.png 512-bit | KitGuru https://www.kitguru.net 32 32 Intel ‘Skylake’ processors for PCs will not support AVX-512 instructions https://www.kitguru.net/components/cpu/anton-shilov/intel-skylake-processors-for-pcs-will-not-support-avx-512-instructions/ https://www.kitguru.net/components/cpu/anton-shilov/intel-skylake-processors-for-pcs-will-not-support-avx-512-instructions/#comments Mon, 02 Mar 2015 20:57:40 +0000 http://www.kitguru.net/?p=238227 Intel Corp.’s forthcoming central processing units code-named “Skylake” for personal computers will not support any AVX-512 instructions, according to a media report. Only Xeon processors for servers and, possibly, workstations will support 512-bit instructions. Support of 512-bit SIMD instructions – known as AVX3 – was expected to be a key feature of Intel “Skylake” processors, …

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Intel Corp.’s forthcoming central processing units code-named “Skylake” for personal computers will not support any AVX-512 instructions, according to a media report. Only Xeon processors for servers and, possibly, workstations will support 512-bit instructions.

Support of 512-bit SIMD instructions – known as AVX3 – was expected to be a key feature of Intel “Skylake” processors, which would help the chips to demonstrate extremely high performance in applications that take advantage of the innovation. However, Intel decided not to enable any AVX-512 instructions in consumer versions of the code-named “Skylake” processors, reports Bits & Chips web-site. While future Xeon chips that belong to the “Skylake” generation will support select AVX-512 instructions. Apparently, even Xeon processors featuring the new cores will not support certain 512-bit instructions supported by Xeon Phi “Knights Landing” co-processors.

intel_core_i7_haswell_edited

As it turns out, only “Cannonlake” processors due in late 2016 or early 2017 will support most AVX-512 instructions, but not all of them. It is also unclear whether consumer versions of “Cannonlake” CPUs will have comprehensive support of 512-bit instructions.

intel_skylake_instructions

Several years ago it was reported that Intel Xeon processors with “Skylake” micro-architecture will support AVX 3.2 technology with 512-bit instructions. Intel Xeon Phi “Knights Landing” is expected to support AVX 3.1 instructions.

intel_cpu_mic_roadmap

While 512-bit instructions will be useful for high-performance computing applications, in client PCs they could improve performance of demanding multimedia applications. Exclusion of AVX-512 support from consumer processors will slowdown adoption of the new instructions by software developers. In fact, without AVX 3.2 the new “Skylake” processors will bring almost no innovations compared to “Haswell” and “Broadwell” chips from instruction-set point of view.

Intel did not comment on the news-story.

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KitGuru Says: Intel’s decision not to enable 512-bit instructions on consumer “Skylake” processors is clearly a strange one. The hardware to support AVX-512 is in the processors and it is unlikely that it uses so many transistors that disabling this technology dramatically improves yields of Intel’s central processing units.

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AMD’s ‘Zen’ could sport Intel’s ‘Skylake’ features, new 512-bit FPU – rumours https://www.kitguru.net/components/cpu/anton-shilov/amds-zen-could-sport-intels-skylake-technologies-new-512-bit-fpu-rumours/ https://www.kitguru.net/components/cpu/anton-shilov/amds-zen-could-sport-intels-skylake-technologies-new-512-bit-fpu-rumours/#comments Sat, 21 Feb 2015 15:53:46 +0000 http://www.kitguru.net/?p=236912 Although microprocessors based on AMD’s next-generation high-performance micro-architecture code-named “Zen” are more than a year away, some details regarding the forthcoming chips and “Zen” in general are beginning to surface. The most recent rumours about the new architecture add some technical details and point to release schedule of the new chips. As reported, the first …

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Although microprocessors based on AMD’s next-generation high-performance micro-architecture code-named “Zen” are more than a year away, some details regarding the forthcoming chips and “Zen” in general are beginning to surface. The most recent rumours about the new architecture add some technical details and point to release schedule of the new chips.

As reported, the first central processing units to use “Zen” for client PCs will be the code-named “Summit Ridge” chip that is expected to feature up to eight cores, a DDR4 memory controller, a PCI Express 3.0 controller and up to 95W thermal design power. It is projected that the chip will be made using 14nm FinFET process technology by GlobalFoundries or Samsung Electronics. Based on unofficial information, AMD’s “Summit Ridge” processors will hit the market in the third quarter of 2016.

amd_fusion_apu_chip_1

Servers first

WccfTech reports citing its own sources that with “Zen” AMD will return to its traditional practice of introducing server processors powered by the latest micro-architectures first and then follow with chips for client PCs. There are no exact schedules given, but taking into account relatively slow ramp up of server processors and platforms by server makers, if AMD wants to find its new Opteron chips in 2016 servers in more or less significant quantities, it will have to introduce its new CPUs in the first half of the year.

amd_server-room

Since eight cores inside the “Summit Ridge” are not enough for modern servers, AMD will either continue to use multi-chip-module design for Opteron processors based on “Zen” architecture next year and onwards (to get a many-core CPU out of two multi-core dies), or will make a separate multi-core design specifically for servers. In fact, AMD has had a technology to build “native” 16-core Opteron processors featuring “Bulldozer”-class dual-core modules for quite a while, but it is unknown whether it will use it even for its forthcoming chips featuring the new micro-architecture.

amd_opteron_chips

Keeping in mind that actual x86 cores are not large and the fact that AMD will utilize 14nm FinFET process tech (albeit with 20nm BEOL interconnect flow and hence appropriate geometries) to make “Zen”-based products, it is possible that AMD will go for native many-core design for server processors if the cores are compact enough and the company finds this a viable and cost-effective solution.

“Skylake” instructions inside “Zen” point to a new FPU

The new micro-architecture from AMD promises to be very different from the company’s current-generation “Bulldozer”-class designs, but almost nothing is known about “Zen” outside of Advanced Micro Devices at present. Without providing any details, the aforementioned media report claims that the new architecture features certain technologies found in the upcoming Intel “Skylake” processors.

Keeping in mind that AMD cannot copy Intel’s designs or even parts of it (in accordance with its x86 cross-license agreement with Intel), do not expect AMD to incorporate any of Intel’s micro-architectural know-hows into its chips. However, what AMD can do is to implement any x86/x87 extensions, enhancements as well as various new instructions introduced by Intel in its central processing units. Intel can do the same too, just like it did with x86-64 more than a decade ago. While we do not know all peculiarities of “Skylake”, many official and semi-official revelations indicate that the new micro-architecture from Intel will bring support of such technologies as AVX 3.2 (512-bit instructions), SHA extensions (SHA-1 and SHA-256, secure hash algorithms), MPX (memory protection extensions), ADX (multi-precision add-carry instruction extensions) and other innovations. AMD has rights to incorporate all of them into its micro-architectures, which it will likely do eventually.

intel_cpu_mic_roadmap

If AMD proceeds with implementation of AVX 3.2 technology, it will have to develop a brand-new floating-point unit (FPU) to execute 512-bit instructions. At present AMD’s FPU features two 128-bit FMAC (fused multiply–add capability) pipelines that can be unified into one large 256-bit-wide unit if one of the integer cores dispatches an AVX instruction. While this approach technically works for AVX and floating-point operations (but AVX execution is dramatically slower on AMD's chips compared to Intel's chips), the AVX 2 further expands usage of most vector integer SSE and AVX instructions to 256 bits, which normally requires a new FPU. 512-bit AVX 3.2 instructions will entail further refinements of hardware, therefore, AMD’s “Zen”, if it supports AVX 3.2, will need an all-new FPU that will hardly resemble that of the “Bulldozer”. Basically, if AMD does not want to repeat the same mistakes it has done with “Bulldozer”, it will need a fully-fledged 512-bit FPU in “Zen” microprocessors. Otherwise, execution of 512-bit AVX 3.2 instructions will be awfully slow.

Summing up

The fact that AMD plans to first release Opteron chips featuring “Zen” cores and only then integrate its new cores into consumer products indicates that the company expects a lot from the micro-architecture which development is currently led by Jim Keller, a legendary CPU architect.

If AMD’s forthcoming “Zen” technology supports everything (or even the majority of) instructions introduced by Intel’s “Skylake” processors in the second half of next year, this will be a significant leap for AMD.

amd_apu_beema_mullins_puma_jaguar_x86_fusion

When it comes to performance, it is logical to expect a substantial increase of performance from AMD’s forthcoming microprocessors. At present we have no idea from where performance improvements will come from exactly. However, a new “fat” FPU in 2016 is not only a logical thing to expect, but rather a must have feature.

AMD did not comment on the news-story.

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KitGuru Says: Keep in mind that many of the things discussed here are speculations based on reports from unofficial sources. We do not know for sure that AMD plans to support AVX-512 in any form next year, we also have no idea which segments of the server market the company would like to address with its Opteron “Zen” processors first in 2016. All-in-all, take everything with a grain of salt.

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Intel details Xeon Phi ‘Knights Landing’ co-processor for HPC https://www.kitguru.net/components/cpu/anton-shilov/intel-details-xeon-phi-knights-landing-co-processor-for-hpc-applications/ https://www.kitguru.net/components/cpu/anton-shilov/intel-details-xeon-phi-knights-landing-co-processor-for-hpc-applications/#comments Thu, 26 Jun 2014 22:50:25 +0000 http://www.kitguru.net/?p=200291 At the International Supercomputing Conference in Leipzig, Germany, Intel Corp. unveiled additional details regarding its next-generation Xeon Phi co-processor code-named “Knights Landing.” As it appears, the KNL chip will not only offer breakthrough performance, but it will also provide breakthrough programmability thanks to the fact that it will feature modern cores with the Silvermont micro-architecture. …

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At the International Supercomputing Conference in Leipzig, Germany, Intel Corp. unveiled additional details regarding its next-generation Xeon Phi co-processor code-named “Knights Landing.” As it appears, the KNL chip will not only offer breakthrough performance, but it will also provide breakthrough programmability thanks to the fact that it will feature modern cores with the Silvermont micro-architecture.

Intel Xeon Phi “Knights Landing” co-processors will be based on the Atom cores powered by the Silvermont micro-architecture enhanced with four-thread per core multi-threading technology as well as AVX512 instructions. Previously Intel used rather outdated Pentium-like (P54C-like) cores in its Xeon Phi co-processors. The new processing engines will help the company to increase single-thread performance of the new accelerators by up to three times compared to predecessors, which will allow to run more sophisticated applications and eventually solve more complex tasks. The new “Knights Landing” co-processors will feature up to 60 cores and will provide up to 3TFLOPS of SP/DP performance. The chips are to be made using 14nm process technology.

intel_xeon_phi_knights_landing

The new KNL co-processors will sport high-speed Omni Scale fabric that will be integrated on-package. This integration along with the fabric's HPC-optimized architecture is designed to address the performance, scalability, reliability, power and density requirements of future HPC deployments. The same fabric will be integrated into the next-generation Intel Xeon central processing units (CPUs) that will be made using 14nm fabrication process.

As reported, the Xeon Phi “Knights Landing” will come with up to 16GB of high-bandwidth on-package memory, which will boost performance of memory bandwidth-dependent applications. This on-package memory will transform KNL chips into independent compute building blocks with massive resources. It is likely that the new Xeon Phi will rely on Micron Technology’s hybrid memory cube (HMC) stacked DRAMs.

intel_xeon_phi_knights_landing_1

Intel Xeon Phi “Knights Landing” co-processors will be available in both PCI Express card and standalone processor form-factors. The latter will be compatible with Intel Xeon sockets.

“Intel is re-architecting the fundamental building block of HPC systems by integrating the Intel Omni Scale fabric into Knights Landing, marking a significant inflection and milestone for the HPC industry,” said Charles Wuischpard, vice president and general manager of workstations and HPC at Intel. “Knights Landing will be the first true many-core processor to address today's memory and I/O performance challenges. It will allow programmers to leverage existing code and standard programming models to achieve significant performance gains on a wide set of applications. Its platform design, programming model and balanced performance makes it the first viable step towards exascale.”

Intel Xeon Phi processor code-named “Knights Landing” is scheduled to power HPC systems in the second half of 2015.

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KitGuru Says: While Intel continues to be relatively tight-lipped about technical specifications of the Xeon Phi “Knights Landing,” it is obvious that the new chip truly changes the game when it comes to high-performance computing. Thanks to integrated high-performance fabric, high-bandwidth memory and modern x86 cores, the KNL solutions will offer a lot of advantages both from performance and programmability points of view.

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