The future of memory for our phones, ultra-thin laptops, and a new wave of AI devices just got a lot clearer. JEDEC has officially published its next-generation JESD209-6 LPDDR6 memory standard. This isn't just an incremental update; LPDDR6 is engineered from the ground up to deliver a significant leap in performance, power efficiency, and security to meet the demands of artificial intelligence and other high-performance workloads.
The standard moves to a dual sub-channel design on each die, with each sub-channel featuring 12 data signal lines. This approach allows for more flexible and efficient operation, boosting performance while maintaining the fine-grained 32-byte data access needed for modern SoCs. The design optimises the command and address signal layout to minimise the physical ball count on the chip, which in turn helps speed up data access and reduce latency.
JEDEC has also baked in a host of new power-saving features. LPDDR6 operates at a lower voltage than its predecessor and introduces more sophisticated power management. A new feature called Dynamic Voltage and Frequency Scaling for Low Power (DVFSL) allows the memory to reduce its supply voltage during low-frequency operation, sipping less power when performance isn't critical. The standard also refines its efficiency modes, allowing the system to use a single sub-channel interface for low-bandwidth tasks, further cutting down on energy consumption.
Lastly, security and reliability components have also been given a significant overhaul. The LPDDR6 standard introduces several new safeguards to maintain data integrity and system stability. One of these is Per Row Activation Counting (PRAC), a mechanism designed to protect against potential data corruption in the DRAM itself. The standard also mandates support for on-die error correcting code (ECC) and includes new capabilities for command and address parity, error scrubbing, and built-in self-testing.
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KitGuru says: When do you expect to see the first devices using LPDDR6 memory?