The blueprint for AMD's next generation of CPUs is beginning to take shape, with a new leak providing a detailed look at the process nodes that will work as the foundation for the upcoming Zen 6 architecture.

According to Kepler_L2 (via 3DCenter), AMD has shared its process node plans with partners, revealing a strategy that leans heavily on TSMC's advanced N2P node for high-performance parts, while utilising N3P for more mainstream and mobile products. Starting with the server segment, both the standard EPYC “Venice Classic” and the high-density “Venice Dense” processors are slated to use TSMC's N2P node. This aligns with previous rumours that AMD is looking to increase core counts, with the 2nm-class node providing the necessary transistor budget for the rumoured 12-core “Classic” and even 32-core “Dense” Zen 6 chiplets.

Desktop gamers and high-end chips will also probably be based on the same node as their server counterparts. The next-generation Ryzen platform, codenamed “Olympic Ridge”, is also set to have its core chiplets built on the N2P node. This will extend to high-end laptops, with the “Gator Range” platform also leveraging N2P for higher-tier mobile solutions.

Things get more mixed in the mainstream laptop segment with the “Medusa Point”, the successors to the current “Strix Point” family. Here, AMD will reportedly employ a mixed approach. For the top-tier Medusa Point SKUs, the processor will be a chiplet design, combining an N2P-based CCD with an I/O die (IOD) manufactured on the N3P node. Further down the stack, the lower-end Medusa Point SKUs are expected to be monolithic chips built entirely on the N3P process.

While this latest leak provides a great deal of clarity on the CPU side, other codenames like the high-end mobile “Medusa Halo” and low-end “Bumblebee” are also being mentioned, though details are scarce. As for the next-generation RDNA5 graphics architecture, sometimes referred to as UDNA, its process node remains unconfirmed.

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