One of the features of Intel Corp.’s Haswell micro-architecture (and Broadwell micro-architecture) were transactional synchronization extensions (TSX), which could significantly boost performance in multi-threaded applications that take advantage of them. As it appears, usage of the technology leads to unpredictable PC behaviour due to an erratum. As a result, Intel this week started to disable the tech using a microcode update.
Intel TSX provides a set of instruction set extensions that let software developers to identify regions of code for transactional synchronization. Programmers can use the TSX to achieve the performance of fine-grain locking while actually programming using coarse-grain locks. With transactional synchronization, the hardware can control dynamically whether threads need to serialize through lock-protected critical sections, and perform serialization only when required. This allows the processors to expose and exploit concurrency that would otherwise be hidden due to dynamically unnecessary synchronization. In general, TSX is aimed at server applications and hardly will be needed by consumers.
Unfortunately, the implementation of the TSX in the Haswell, Haswell-E, Haswell-EP and client Broadwell microprocessors contained an error, or erratum, which can cause instabilities. According to Intel, under a complex set of internal timing conditions and system events, software using the TSX instructions may result in unpredictable system behavior.
The bug was reportedly discovered by a software developer and caused Intel to disable the technology by updating CPU microcode using BIOS updates. Intel will let developers to re-enable the TSX in BIOS so to write code for future processors, such as Haswell-EX, Broadwell-EP, Broadwell-EX and other. However, the tech will be disabled for typical users in order to avoid instabilities.
Erratums are often found in multiple microprocessors. Sometimes they cause chipmakers to even recall their products (Intel had to recall the original Pentium chips, whereas AMD had to recall its Opteron “Barcelona” processors in the past), but in many cases certain functions of central processing units just get disabled using a micro-code update.
Intel remains committed to the TSX instructions in the long run, so the technology will be enabled in future chips. However, new-generation mainstream servers will not get it.
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KitGuru Says: While erratums have emerged in the past, with Haswell and Broadwell Intel seems to have experienced a lot of small problems that do not impact its business performance significantly, but makes us think about viability of the Tick-Tock strategy in general. Under the Tick-Tock plan, the company just has to introduce something new every year. In many cases it means rather tight schedules for everyone, which may cause things like limited overclocking potential of Intel’s Haswell, issues with 14nm process technology or the TSX erratum.Intel finds erratum in Haswell and Broadwell chips, disables TSX instructions,