PCI-SIG releases PCIe 8.0 draft with up to 1TB/s via x16

PCI-SIG has announced the release of the PCIe 8.0 draft specification version 0.5. The update confirms the technical target of 256.0GT/s raw bit rate, providing up to 1TB/s of bidirectional bandwidth in an x16 lane configuration. A significant focus of this draft is evaluating new connector technology to support increased bandwidth requirements.

The organisation notes that the current physical layer and traditional copper-based electrical connections are approaching saturation limits. While previous generations maintained the familiar slot design, PCIe 8.0 may require a replacement for the standard connector to achieve its performance targets. Despite the potential for a new physical interface, PCI-SIG intends to maintain backward compatibility with previous PCIe generations.

The PCIe 8.0 specification is scheduled for finalisation by 2028. Deployment is expected to begin with server-class hardware from AMD, Intel, and Nvidia before transitioning to the consumer ecosystem in the following decade. The performance targets represent an eightfold increase in bandwidth over the current PCIe 5.0 standard used by modern GPUs.

Design goals for the final v1.0 specification include meeting strict latency, FEC, and reliability targets. Additionally, the standard aims to improve bandwidth through protocol enhancements and implement new techniques to reduce overall power consumption.

KitGuru says: When do you expect to see the first PCIe 8.0 devices launch into the market?

Become a Patron!