Taiwan Semiconductor Manufacturing Co. this week denied any delays of risk or mass production of chips using its 10nm process technology. The company intends to start volume production of semiconductors at 10nm node late next year, which means that its clients will receive their first 10nm chips in the first quarter of 2017.
“The recent progress of our 10 nanometer technology development is very encouraging and on track with our plan,” said Mark Liu, president and co-CEO of TSMC, during the company’s earnings conference call with investors and financial analysts. “Technology risk start qualification is targeted at the end of this year, followed by many customer’s product qualifications. Our volume production is planned to start from the end of 2016.”
It should be noted that the start of production does not mean commercial shipments. Production cycle of an advanced chip made using 10nm FinFET process technology will likely exceed 100 days from wafer start to chip delivery, which means that the company will be able to ship the first batch to its customer(s) only in Q1 2017. TSMC will start high-volume production of chips using its 10nm process only in late Q1 or sometime in Q2 2017.
“We ramp up 10nm in the Q4 2016 next year, but the real product shipment will be in Q1 2017,” said C.C. Wei, president and co-CEO of TSMC.
TSMC discloses different target characteristics of its 10nm FinFET (CLN10FF) manufacturing technology on different occasions, which indicates that they may not be finalized.
At present, the contract maker of semiconductors believes that its 10nm FinFET (CLN10FF) fabrication process will have 110 – 120 per cent higher transistor density compared to its 16nm FinFET+ (CLN16FF+) process tech, 15 per cent higher frequency potential at the same power and 35 per cent lower power consumption at the same frequency and complexity. Previously the company disclosed more optimistic expectations regarding clock-rates and power.
With 10nm process technology, TSMC obviously concentrated mostly on increasing transistor density so that to decrease per-transistor costs of ICs made using the technology. Since TSMC’s 16nm processes rely on back-end-of-line interconnect flow originally developed for 20nm process, chips produced at 16nm node are not smaller than ICs [integrated circuits] made using 20nm tech. For many fabless semiconductor companies TSMC’s 16nm manufacturing technologies are too expensive because of high per-transistor costs as well as extreme design costs associated with FinFETs in general.
Performance improvements of TSMC’s 10nm fabrication tech compared to the company’s 16nm FinFET+ are not really impressive. In fact, the CLN16FF+ has similar advantages – up to 15 per cent higher clock-rate or up to 30 per cent lower power consumption – over the CLN16FF.
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KitGuru Says: While TSMC may start volume production of 10nm chips a little earlier than Intel, its CLN10FF fabrication technology will not help to significantly decrease power consumption or increase frequencies of processors. On the other hand, TSMC may introduce a better version of its 10nm manufacturing process later…