The AMD FX 8150 processor ships in a very artistic box with the words ‘Black Edition’ featuring on the front. This means that the processor is unlocked, to make sure the overclocking experience is as easy as possible.
|Processor Model||CPU Base||CPU Turbo Core||CPU Max Turbo||TDP||Cores||L2 Cache||L3 Cache||Max DDR3||PKG||NB|
The FX-8150 slots in right at the top of the new FX range.
The FX 8150 is based around an 8 core design… the world’s first 8 core desktop chip. It runs with a base frequency of 3.6ghz, and can turbo right up to 4.2ghz. If you are mathematically challenged, this translates to a 600mhz boost.
Above, we have listed CPU Turbo Core speeds of 3.9ghz and ‘max turbo’ speeds of 4.2ghz.
Above, we took a screenshot during an encoding task, and we can see that the multiplier has increased to 19.5x, giving a clock speed of 3.9ghz, matching the AMD Turbo core figure.
The design offers new instruction support for FMA4, XOP, AES, AVX, and SSE 4.2, for next generation PC applications.
The Bulldozer Concept was realised with a 2 core design which could share the hardware when the demand was based around a single thread. The engineers wanted a hardware design which would have little impact on the timing and complexity of critical paths. A structure which would also benefit from increasing the amortized bandwidth. AMD designed the chip so it could utilise the shared bandwidth with a targeted feature set to benefit both threads.
Bulldozer is a ‘monolithic’ dual core building block which can support two threads of execution. It shares latency tolerant functionality with dynamic resource allocation between threads. In real world terms this offers greater scalability and predictability than two threads sharing a single core.
The design also has bandwidth related advantages for multi threaded situations without significant loss on serial single threaded workload components. Another benefit is that when only one thread is active, it can get access to all the shared resources.
The Bulldozer front end modules can decode up to 4 instructions per cycle, which compares to 3 on the previous generation Phenom II processors.
The shared front end features decoupled predict and fetch pipelines with a prediction directed instruction prefetch design. This is fed into the dedicated cores which feature a unified scheduler per core and a way predicted 16k byte L1 Dcache.
The shared FPU features co processor organisation and reports the completion of tasks back to the parent core. There are dual 128 bit packed integer pipes and a unified scheduler for both threads. The chip has a 16 way unified L2 cache.
AMD are using the same die for their desktop and server products, each Bulldozer module has two cores, for a total of eight. Zambezi, Interlagos and Valencia chips all follow this structure.
Above, a breakdown of the chip structure. There is 128kb of Level1 data cache, split into 16kb per core. There is 256k of Level 1 instruction cache, split into 64kb per module. Finally there is a 8MB of Level 2 cache, split into 2 MB per module.
The Integrated Northbridge controls a total of 8MB of Level 3 cache, with two 72 bit wide DDR3 memory channels and four 16 bit HyperTransport links. AMD have attempted to minimise the silicon area by sharing functionality between two cores, and circuits are power gated dynamically to help improve power efficiency.
The AM3+ platform offers support for CPU voltage loadline as well as increases in both ILDT current and DRAM current. This will help improve HyperTransport link speeds. Out of the box memory support extends to DDR3 1866mhz speeds.