UPDATE: The original story stated that it described an implementation of an AMD microprocessor based on “Zen” micro-architecture. In fact, the story describes one “Zen” core.
Although there are a lot of rumours about AMD’s next-generation code-named “Zen” microprocessors, there are not a lot of official or even semi-official details about the chips. On Monday an alleged AMD employee posted what appears to be a slide from AMD’s presentation containing a block diagram of one “Zen” microprocessor core.
The block diagram, which details a core of AMD’s “Summit Ridge” microprocessor, reveals that the execution unit will have six integer pipelines as well as two non-shared 256-bit floating point units (FPUs). Previously it was reported that the “Summit Ridge” chip has eight cores, dual-channel DDR4 memory controller as well as 95W thermal design power. The image was published in Planet3DNow.de forums by an anonymous poster.
At present AMD’s FPU features two 128-bit FMAC (fused multiply–add capability) pipelines that can be unified into one large 256-bit-wide unit if one of the integer cores dispatches an AVX instruction. While this approach technically works for AVX and floating-point operations, it is not very efficient: AVX execution is dramatically slower on AMD’s chips compared to Intel’s chips.
Two 256-bit FPUs mean that AMD’s future microprocessors based on “Zen” micro-architecture will significantly improve performance in applications that use floating point units as well as heavily rely on AVX instructions. Moreover, theoretically, two 256-bit FPUs could support 512-bit AVX instructions.
AMD did not comment on the news-story.
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KitGuru Says: It looks like AMD plans to reveal the first official set of details about “Zen” at its financial analyst day next week. It is very likely that in addition to basic things about the new processors, the company will also disclose more details about the CPUs. Given the fact that AMD should already have the first working samples of “Summit Ridge”, it is possible that AMD will also demonstrate the chips in action.