Intel has revealed more details about its upcoming Tiger Lake CPU architecture. During a presentation at Hot Chips 2020, Intel revealed the die of a quad-core Tiger Lake processor and shared new information on the architecture’s specifications and power management.
Intel Tiger Lake is the company’s latest mobile focused architecture. Through the use of 10nm SuperFIN transistors and SuperMIM technology, Intel claims that these revised transistors will offer a performance bump typical of a new process node. Intel’s new architecture will support up to LPPDR5-5400 memory and PCIe 4.0 and will be equipped with Willow Cove Cores and Xe Graphics.
Unfortunately, Intel hasn’t divided the die sections in the image, but the die analyst @Locuza_ tweeted its interpretation of the die. By looking at it, we see that Intel reserved a significant part of the die for the Xe Graphics iGPU, located on the right side of the die. From the image, it seems that this iGPU feature 96EUs.
Image Credit: @Locuza_
We should also point to the four Willow Cove cores in blue, each with their respective cache structure, totalling 5MB of L2 cache, and 12MB of L3 cache. The image also shows 4x on-die Thunderbolt 4 ports, multiple I/0 interfaces, and the ring agent that connects the iGPU to the CPU and to the those same I/O interfaces.
As we know, Tiger Lake will be the first mobile architecture featuring the power-hungry PCIe Gen4. To fight the increase in power consumption, Intel will be using DVFS (Dynamic Voltage/Frequency Scaling). By dividing the CPU into power domains – core, fabric, and memory – the SoC manages the power of each section individually depending on the workload. For example, during a core-centric workload, the SoC can reduce the power provided to the fabric/memory and allocate it to the core.
KitGuru says: Are you interested in Intel’s Tiger Lake architecture? Will they provide tough competition for AMD’s Ryzen 4000 mobile CPUs?