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TSMC and ARM showcase first 7nm chiplet system for HPC

ARM and TSMC have announced their co-developed silicon-proven chiplet system based on multiple ARM cores, using TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) packaging solution, which is heralded as an industry first based on the 7nm FinFET process.

The proof-of-concept chip comprises of a dual-chiplet CoWoS implemented in 7nm. Each chiplet contains four ARM Cortex-A72 processors, with an on-die interconnect mesh bus operating at 4GHz. The system also features a unique Low-voltage-IN-package-INterCONnect developed by TSMC to reach data rates of 8Gb/s per pin and offers excellent power efficiency as a result.

TSMC’s Low-voltage-In-package-INterCONnect or LIPINCON for short, operates at 0.3v and achieves 8GT/s (Giga Transactions per second) and 320GB/s bandwidth. Bandwidth density is listed as being 1.6TB/s/mm² with 0.56pJ/bit (pico-Joules per bit) power efficiency. As a comparison, AMD’s Infinity Fabric consumes ∼2pj/bit, while Intel has claimed as low as 0.3pJ/bit for EMIB, and 0.5pJ/bit for MDIO.

This new chiplet concept showcases ARM and TSMC’s potential to provide technologies to high-performance computing (HPC) applications. ARM and TSMC developed this design as an alternative to traditional SoCs which are both difficult and expensive to manufacture with decent yields.

Rather than relying on the traditional SoC approach, which combines every system component onto a single die, the chiplet partitions large multi-core designs into smaller chipsets. This offers a more efficient approach for functions to be split into smaller dies, allowing each chiplet to be produced with different process technologies.

The major significance in this new design is the fact that now TSMC’s proof-of-concept LIPINCON interconnect technology is proven to work. So customers will be able to take advantage of it and it could find its way into commercial HPC products in the future.

KitGuru says: Both ARM and TSMC have now proven they are capable of making an efficient HCP capable chiplet design. What does this mean for HPC systems and future partnerships between the two?

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