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PCI-SIG announces official specifications for PCIe 6.0

PCIe 5.0 connectivity has only just hit the market thanks to Intel’s Alder Lake platforms. However, PCI-SIG, the consortium responsible for specifying the PCI connectivity standards, has already shared the official specifications of  the PCIe 6.0 interface.

Three years have passed since PCI-SIG announced the PCIe 5.0 standard. Now, the consortium has come out to publicly announce its successor, PCIe 6.0. As per its specifications, the new standard was built to provide two times more data rate than PCIe 5.0, up to 64GT/s, and a maximum bidirectional bandwidth of up to 256 GB/s for x16 lanes (8GB/s per lane).

The new standard’s design also offers lower latency thanks to the fixed-size Flow Control Unit (Flit)-based encoding, capable of leveraging Pulse Amplitude Modulation with 4x levels (PAM4) signalling. In addition, its uses Forward Error Correction (FEC) and cyclic redundancy check (CRC) to diminish the increased bit error rate characteristic from PAM4 signalling.

Like the previous standards, the 6th generation will be backwards compatible with older PCIe technologies, ensuring users can use older devices on new interfaces.

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KitGuru says: Now that PCIe 6.0 has been announced, Nvidia, Intel and AMD may well update their roadmaps with the latest PCIe technology. If history serves as a lesson, it will take some time before any of them officially announce a platform supporting the new standard. Still, rumours about upcoming platform support are already out in the wild.

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