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Intel confirms delay of 10nm chips to 2017, blames difficulties

Intel Corp. on Wednesday confirmed the delay of mass production of central processing units using 10nm fabrication process to 2017. The company said that it ran into difficulties with its 10nm technology and decided to stretch the life-cycle of 14nm process with one more family of CPU products code-named “Kaby Lake”. Intel admitted that it now takes about 2.5 years to transit from one manufacturing technology to another, which means the stretch of Moore’s law cadence.

When Gordon Moore first did his observation regarding doubling the number of transistors in an integrated circuit in 1965, he noted that they increase two fold every 12 months. In 1975, he updated his estimate and revised the forecast doubling time to two years. However, in the recent years manufacturing technologies and semiconductors became so complex that it led to a stretch of manufacturing technology transitions. Consequently, the amount of transistors per chip now doubles every 2.5 years. As a result of the stretch of Moore’s law cadence, Intel now needs to introduce not two, but three processor families made using the same process technology.

“To address this cadence, in the second half of 2016 we plan to introduce a third 14nm product code-named Kaby Lake, built on the foundations of the Skylake micro-architecture, but with key performance enhancements,” said Brian Krzanich, chief executive officer of Intel, during the company’s quarterly conference call with investors and financial analysts. “We expect that this addition to the roadmap will deliver new features and improved performance and pave the way for a smooth transition to 10nm.”

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The company intends to start production of its code-named “Cannonlake” processors made using 10nm manufacturing technology only in the second half of 2017. The world’s largest chipmaker believes that the additional year will help it to polish-off its 10nm fabrication process and ensure a high-volume launch of new chips.

“In the second half of 2017, we expect to launch our first 10nm product code-named Cannonlake,” said Mr. Krzanich. “When we say second half of 2017, we are talking about millions of units and large volumes.”

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Mr. Krzanich did not reveal a lot of details about the company’s 10nm fabrication process and the exact reasons of the delay, but he implied that the new manufacturing technology uses FinFET transistors with enhancements and immersion lithography with a lot of multi-pattern steps.

“Each [process technology] has its own recipe of complexity and difficulty,” explained Mr. Krzanich, who once was responsible for manufacturing operations at Intel. “14nm to 10nm is the same thing that happened with 22nm to 14nm [transition]. The lithography is continuing to get more difficult as you try [to scale down]. The number of multi-pattern steps you have to do is increasing. This is the longest period of time without a lithography node change.”

The chief executive of Intel also implied that the company will not take any shortcuts just to get to 10nm in time. The new process will feature smaller transistor fin pitch, transistor gate pitch as well as interconnection pitch compared to 14nm technology in a bid to maximize transistor density.

“We believe if you take a look at the scaling, it will be quite strong relative to the normal scaling parameters that occur with the Moore’s Law transition,” said the head of Intel. “I am not going give you the exact numbers right now. We think if you combine all those together, our leadership position [in the industry] does not change, even with this date.”

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Intel said that while for now its manufacturing technology cadence is stretched to essentially 2.5 – 3 years, the company will try to go back to its two years cadence. Quite possibly, the return of the problematic “tick-tock” cadence will require a switch to extreme ultraviolet lithography. If the company’s 10nm process tech will be used to produce three product families (i.e., for three years), then EUV will likely become a viable option for 7nm sometimes in 2020.

It should be noted that stretching process technology cycles also mean stretching micro-architectural cycles. It remains to be seen how Intel will manage to improve performance from one processor generation to another and how significant performance improvements will be going forward.

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KitGuru Says: It looks like “Cannon Lake” processors have not been cancelled, but delayed by one year. If it is the case, then the rumoured “Ice Lake” chips may replace them in 2018, if Intel decides to stretch life-cycle of 10nm to three generations. Alternatively, “Ice Lake” may  not emerge at all because using one micro-architecture for four years is not a good thing in general. Moreover, Intel may not need to use 10nm for three generations if EUV becomes viable by 2019.

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