Intel Corp. is working on a brand-new server platform code-named “Purley”, which will include Xeon microprocessors based on the “Skylake” micro-architecture with up to 28 cores and will feature a number of platform-level innovations. The new multi-core chips will not only sport extraordinary amount of cores and new features, but will also get physically bigger than today’s chips, making server infrastructure considerably more complex.
Intel “Purley”: Biggest platform advancement in a decade
The “Purley” platform will be Intel’s biggest server platform advancement in many years, when the world’s largest chipmaker rolls it out in 2017. Intel’s “Purley” will be a highly-configurable platform designed for enterprise, cloud, HPC [high-performance computing], storage and network applications. Intel “Purley”-based supercomputers are expected to finally hit ExaFLOPS performance late this decade.
The platform will support dual-socket (2S), quad-socket (4S) as well as octa-socket (8S) machines and will rely on Intel’s next-generation a point-to-point processor interconnect UPI (Ultra Path Interconnect) bus, which will replace the company’s current-gen QuickPath Interconnect (QPI) technology.
At present, not a lot is known about Intel’s next-generation UltraPath Interconnect (UPI) technology (also known as KTI or Keizer Technology Interconnect), except the fact that it will operate at 9.6GT/s or 10.4GT/s data-rates and will be considerably more efficient than today’s QPI since it will support multiple requests per message.
The “Purley” server platform will be the first to support six-channel memory per socket, which will provide massive amount of bandwidth to each processor. Besides, the new platform will also be the first to support Intel’s OmniPath 100Gb/s fabric to connect for external compute and I/O nodes, which will greatly increase performance in supercomputer applications.
Intel Xeon “Skylake”: 28 cores, 6-channel DDR4 memory, Omni-Path fabric
Intel will release three different versions of Xeon processors for its “Purley” platform targeting different applications two years from now – “Skylake-EP”, “Skylake-EX” and “Skylake-F” – according to a report from CPU World. The new chips will feature up to 28 cores based on the “Skylake” micro-architecture with AVX512 instructions and Hyper-Transport technology, up to six DDR4 memory channels (up to two 2400MHz DIMMs per channel are supported, i.e., up to 768GB of DDR4 memory per socket without SMB), up to 48 PCI Express 3.0 lanes as well as two or three UPI channels per socket.
- Intel Xeon “Skylake-EP” processors will be aimed at mainstream dual-socket (2S) servers and will thus only have two UPI links. Thermal design power of low-power versions of such processors will range from 45W to 80W, whereas standard high-performance offerings will have TDP of up to 145W. Workstation-class offerings with increased clock-rates will be rated to dissipate up to 160W.
- Intel Xeon “Skylake-EX” processors will be designed for high-performance and mission critical machines with two, four or even eight sockets, which means that they will feature up to three UPI links. The processors will introduce new RAS [reliability, availability, serviceability] features such as Instruction Retry (pipeline error protection for integers), Advanced Error Detection and Correction as well as Adaptive Dual Device Data Correction, to make next-gen high-end servers even more robust. According to previously released unofficial information, Intel’s forthcoming expandable processors will support four times higher memory capacity (compared to today’s chips) thanks to “Apache Pass” scalable memory buffer (SMB), which means up to 6144GB (over 6TB) per socket, or up to 24576GB of DDR4 RAM per 4S machine. The “Skylake-EX” chips will have TDP of up to 165W.
- Intel Xeon “Skylake-F” will be aimed at high-performance computing applications (which use 2S platforms) and will incorporate one link of the first-generation OmniPath fabric with 100Gb/s bandwidth. The latter will be supported by the code-named “Storm Lake” chip, which will be incorporated into the Xeon’s multi-chip-module (MCM) package. Among other things, Omni-Path Fabric will be used to connect to next-gen Xeon Phi co-processors.
Thanks to massively higher memory bandwidth, increased core count, improved micro-architecture and 512-bit AVX-3.* instructions, expect Intel Xeon “Skylake” processors to offer dramatically higher performance compared to today’s central processing units for servers. The architecture of the processors will be configurable, hence, Intel will easily tailor it for custom solutions required by its large cloud datacentre clients. Moreover, the new processors are expected to integrate “Cannonlake” graphics cores and media transcode capabilities, at least, optionally.
Intel socket P0: Big CPUs need big sockets
Since the new chips will feature more memory channels, integrated fabric and will be considerably more complex than today’s server microprocessors, Intel will introduce all-new infrastructure for its “Purley” platform.
The upcoming Xeon “Skylake” processors will use the new socket P0 and will feature flip-chip land-grid array packaging (FC-LGA) with up to 3467 contacts. The final amount of pins to be used is unclear today, but according to unofficial information, it will exceed 3000 balls.
The dimensions of the new Xeon processor packages will also be considerably larger compared to today’s LGA2011-3. Intel is currently considering 76mm*51mm or 76mm*56mm sizes, CPU World claims. By contrast, today’s Core i7 Extreme and Xeon E5/E7 chips in LGA2011-3 form-factor feature 58.5mm*51mm component size. Mainstream Intel LGA1150 processor come in 37.5mm*37.5mm packages.
Since packages are going to be used by several generations of chips, Intel has to include support of features for future generation processors.
Intel C620 “Lewisburg”: Massive I/O for massive servers
Intel “Purley” platform will rely on the company’s new C620 “Lewisburg” chipset, which will sport massive amount of improvements compared to today’s C602J and C610 platforms.
The top-of-the-range C620 “Lewisburg” core-logic will use four DMI 3.0 lanes (8GT/s) to connect to CPU and will support four 10GbE ports, 20 PCI Express 3.0 lanes, 14 Serial ATA III ports, 10 USB 3.0 ports, a new Intel QuickAssist accelerator as well as all-new Intel Innovation Engine.
The new QuickAssist accelerator is expected to provide substantially improved acceleration performance: up to 2.5x faster decryption, and up to 4x better compression speed compared to “Coleto Creek” chip used today.
The new Innovation Engine promises to enable server makers to create their own custom remote management solutions and no longer rely solely on Intel’s own Active Management software. The IE is based on a dedicated 32-bit x86 core, which means that it will be rather powerful.
Intel is expected to release its “Purley” platform and Xeon “Skylake” processors in 2017.
Intel did not comment on the news-story.
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KitGuru Says: Without any doubts, Intel’s “Purley” platform will be nothing, but a breakthrough. What is noteworthy is that it will not support PCI Express 4.0, as expected several years ago; integrated silicon photonics and some other things. Nonetheless, when all features of the new platform from Intel are considered, it is obvious that with “Purley” the world’s largest maker of CPUs will again strengthen its positions in the market of servers.